Recently, portable information technology (IT) products such as smartphones, wearable devices, and the like, have been thinned, or produced with increasingly thin dimension. Therefore, the demand of thinning a passive element in order to decrease an overall thickness of a package has increased.
To this end, demand for a thin-film ceramic capacitor capable of implementing a reduced thickness of a package, as compared to a multilayer ceramic capacitor, has also increased.
Meanwhile, in a capacitor product manufactured using thin film technology, a method of forming vias for connections between an external electrode and an electrode layer and between electrode layers may be important. Performance of the thin-film ceramic capacitor is affected by the method of forming the vias as described above and a final structure of the vias.
In a method of manufacturing a thin-film ceramic capacitor according to the related art, at the time of forming vias after repeatedly stacking dielectric layers and electrode layers, one via is required in one electrode layer, and there is provided a method of forming a larger number of vias as compared to the number of electrode layers.
In addition, as a patterning method at the time of stacking the electrode layers, there is provided a method of stacking even-numbered electrode layers and odd-numbered electrode layers in different forms and etching one side surfaces so as to expose only even- or odd-numbered electrode layers and then connecting electrodes to each other.
However, these methods have problems in that processes are complicated, and manufacturing costs may be increased, such that a technology capable of easily manufacturing a more thinned thin-film ceramic capacitor is required.
Meanwhile, at the time of manufacturing the thin-film ceramic capacitor, after forming a plurality of dielectric layers and electrodes, there is a need to form and connect vias in order to connect upper and lower electrodes to each other. In this case, when an area of the via is increased, capacitance of the dielectric layer is decreased in accordance with the increase in the area of the via, and as a size of the via is increased, a problem such as a limitation in design, for example, disposition of the electrodes, or the like, may occur.
Further, in order to connect vias in respective layers to each other, the etching should be performed several times up to an electrode layer, such that process cost may increase.